Pedroni V.A. Finite State Machines in Hardware. Theory and Design (with VHDL and SystemVerilog)

MIT Press, 2013. — 350 p.This book deals with the crucial issue of implementing Finite State Machines (FSMs) in hardware, which has become increasingly important in the development of modern, complex digital systems.
Because FSM is a modeling technique for synchronous digital circuits, a detailed review of synchronous circuits in general is also presented, to enable in-depth and broad coverage of the topic.
A new classification for FSMs from a hardware perspective is introduced, which places any state machine under one of three categories: regular machines, timed machines, or recursive machines. The result is a clear, precise, and systematic approach to the construction of FSMs in hardware.
Many examples are presented in each category, from datapath controllers to password readers, from car alarms to multipliers and dividers, and from triggered circuits to serial data communications interfaces.
Several of the state machines, in all three categories, are subsequently implemented using VHDL and SystemVerilog. It starts with a review of these hardware description languages, accompanied by new, detailed templates. The subsequent designs are always complete and are accompanied by comments and simulation results, illustrating the design’s main features.
Numerous exercises are also included in the chapters, providing an invaluable opportunity for students to play with state machines, VHDL and SystemVerilog languages, compilation and simulation tools, and FPGA development boards. In summary, the book is a complete, modern, and interesting guide on the theory and physical implementation of synchronous digital circuits, particularly when such circuits are modeled as FSMs.The Finite State Machine Approach
Hardware Fundamentals — Part I
Hardware Fundamentals — Part II
Design Steps and Classical Mistakes
Regular (Category 1) State Machines
VHDL Design of Regular (Category 1) State Machines
SystemVerilog Design of Regular (Category 1) State Machines
Timed (Category 2) State Machines
VHDL Design of Timed (Category 2) State Machines
SystemVerilog Design of Timed (Category 2) State Machines
Recursive (Category 3) State Machines
VHDL Design of Recursive (Category 3) State Machines
SystemVerilog Design of Recursive (Category 3) State Machines
Additional Design Examples
Pointer-Based FSM Implementation