Smith D.J. HDL Chip Design. A practical guide for designing, synthezing and simulating ASICs and FPGAs using VHDL or Verilog

Doone Publications, 1996, 555 p.This book is intended for practicing design engineers, their managers who need to gain a practical uderstanding of the issues involved when designing ASiCs and FPGAs, and students alike.
VHDL and Verilog are covered equally throughout this book. Code examples show VHDL on the left and Verilog on the right because VHDL L’ecame a standard first. All language reserved words are shown emboldened. Also, all HDL code related issues in the text apply equally to VHDL and Verilog unless explicitly stated otherwise. Where synthesized circuits are shown they are a result of synthesizing either the VHDL or Verilog version of the associated model.This book is divided into 12 chapters, a glossary and two appendices.