Saxena P., Shelar R.S., Sapatnekar S.S. Routing Congestion in VLSI Circuits: Estimation and Optimization

Springer, 2007. — 254 p. — (Series on Integrated Circuits and Systems). — ISBN 978-0-387-30037-5.With dramatic increases in on-chip packing densities, routing congestion has become a major problem in integrated circuit design, impacting convergence, performance, and yield, and complicating the synthesis of critical interconnects. The problem is especially acute as interconnects are becoming the performance bottleneck in modern integrated circuits. Even with more than 30% of white space, some of the design blocks in modern microprocessor and ASIC designs cannot be routed successfully. Moreover, this problem is likely to worsen considerably in the coming years due to design size and technology scaling.The origins of congestion
An introduction to routing congestion
The estimation of congestion
Placement-level metrics for routing congestion
Synthesis-level metrics for routing congestion
The optimization of congestion
Congestion optimization during interconnect synthesis and routing
Congestion optimization during placement
Congestion optimization during technology mapping and logic synthesis
Congestion implications of high level design